1. Field of the Invention
The present invention relates to a non-volatile memory device, and in particular, to a NOR flat cell mask ROM (Read Only Memory) having a multi-bit cell structure, which can achieve process simplicity, reduce turnaround time and ensure process margin.
2. Description of the Related Art
Semiconductor memory devices are largely divided into RAMs (Random Access Memories) and ROMs (Read Only Memories). RAMs are referred to as volatile memories in that data is destroyed with passage of time. RAMs allow rapid data storage and data retrieval. ROMs retain data once it is entered but perform slow data storage and retrieval.
A mask ROM can be categorized as NOR type or NAND type. The NAND cell structure is used for 4- and 16-Mbit mask ROMs because of its feasibility for high integration because it occupies a small cell area, despite a low cell current. A conventional NOR cell offers high-speed operation due to its high cell current but occupies a large cell area. Thus, the NAND cell structure is widely used in prior systems requiring high integration.
However, a NOR flat cell has been recently developed, which dispenses with a field oxide film for isolating devices in a cell array and can be miniaturized to be as small as a NAND cell, while it still has the advantages of the conventional NOR cell. This NOR flat cell advantageously enables high speed and low voltage operation due to high cell current and cell uniformity and facilitates development of a multi-bit cell (MBC) or a multi-level cell (MLC). A conventional cell stores only "0" and "1". By contrast, the multi-bit cell stores several data types such as "00", "01", "10", and "11", to thereby have a data storage capacity twice as large as that of the conventional cell at a conventional cell integration level. Assuming that the conventional cell integration level is n, the conventional data storage capacity is 2.sup.n. Yet, in the case of a multi-bit cell having four states, each with the cell integration level of n, the data storage capacity is 2.sup.2n. The cell integration level is increased by a factor 2.sup.n, in effect.
FIG. 1 contains a schematic plan view of a conventional NOR flat cell mask ROM. Referring to FIG. 1, the NOR flat-cell mask ROM is a matrix structure in which buried N.sup.+ diffusion layers 12, provided as sources/drains and bit lines of cell transistors on the surface of a semiconductor substrate 10, are arranged in a column direction, extending in a row direction. Gate electrodes 16, provided as gate dielectric layers and word lines, orthogonally intersect the buried N.sup.+ diffusion layers 12. The width of the gate electrodes 16 is the channel width of the cell transistors, and the distance between buried N.sup.+ diffusion layers 12 is the channel length thereof.
In the conventional NOR flat cell mask ROM as mentioned above, data is stored by selectively implementing enhancement ion implantation on a channel area of a cell transistor. The ion implantation generally changes the threshold voltage Vth of the cell transistor. A predetermined voltage is applied to the buried N.sup.+ diffusion layer provided as a bit line, and a ground voltage is applied to an adjacent bit line to drive the cell. Here, if the voltage on a selected word line is lower than the threshold voltage of the cell transistor, a selected cell turns on and the voltage on the bit line is discharged. Thus, the selected cell is read as "on". On the contrary, if the voltage on the selected word line is higher than the threshold voltage, the selected cell turns off and the voltage on the bit line is maintained. Thus, the selected cell is read as "off".
In an exemplary conventional four-state multi-bit programming, the amount of current discharged from the bit line is estimated to determine data types by varying the threshold voltage of the cell transistor to 0.8V, 2.5V, 4.0V, and 6.0V with the voltage on the selected word line swept to 1.6V, 3.3V, and 5.0V. That is, if the cell turns on with the word line voltages of 1.6V, 3.3V, and 5.0V, it is set to states "00", "01", and "11", respectively. If the cell turns off, it is set to state "10".
A cell threshold voltage distribution of the respective states is significant to multi-bit cell programming in that it determines chip characteristics such as sensing margin and speed. That is, data misreading can be avoided in sensing each state only if the difference between the threshold voltages is large. Yet, since increasing both the threshold voltage of a cell transistor and the word line voltage is limited in terms of processing, the cell threshold voltage distribution should be selected in order to load four states within a predetermined threshold voltage range.
FIGS. 2, 3, and 4 contain schematic sectional views referred to for describing a multi-bit programming method in a conventional flat cell mask ROM. Referring to FIG. 2, a buried N.sup.+ diffusion layer 12 is formed on a predetermined area of a P-semiconductor substrate 10, preferably an area for forming a source/drain and a bit line of a cell transistor, by ion implanting an N.sup.+ type impurity in an ion implantation and photolithography process. Then, a gate dielectric layer 14 is formed by thermally oxidizing the surface of the substrate 10. A conductive layer for a gate electrode of the cell transistor is formed on the gate dielectric layer 14 by stacking, for example, an impurity-doped polysilicon layer and a metal silicide layer. Subsequently, a gate electrode of a polycide structure, that is, a word line 16, is formed by patterning the metal silicide layer and the polysilicon layer using photolithography.
Following formation of a first photoresist film pattern 20 to open a predetermined cell by photolithography, a first ion implantation is performed by ion implanting a first impurity 22 onto the substrate surface of the exposed cell with the first photoresist film pattern 20 used as an ion implanting mask. As a result, states having an initial threshold voltage, that is, the lowest threshold voltage (hereinafter, referred to as states "00") due to the channel of the cell masked from the programming ion implantation, and states having the third highest threshold voltage (hereinafter, referred to as states "01"), are programmed.
Referring to FIG. 3, after the first photoresist pattern 20 is removed, a second photoresist film pattern 24 is formed by photolithography to perform a second ion implantation. Then, a second impurity 26 is ion implanted on an exposed substrate surface, using the second photoresist film pattern 24 as an ion implanting mask so that the exposed state "00" changes to a state having the second highest threshold voltage (hereinafter, referred to state "11").
Referring to FIG. 4, after the second photoresist film pattern 24 is removed, a third photoresist film pattern 28 is formed by photolithography to perform a third ion implantation. Then, a third impurity 30 is ion implanted on an exposed substrate surface, using the third photoresist film pattern 28 as an ion implanting mask so that the exposed state "00" changes to a state having the highest threshold voltage (hereinafter, referred to a state "10"). Thus, the cell programming is completed.
While the four states "00", "01", "10", and "11 " are formed using three masks and three ion implantations in the above conventional multi-bit programming method, two masks and two ion implantations are used in another conventional multi-bit programming method. That is, the states "00" and "10" are formed by first and second ion implantations, respectively, and the state "10" can be formed by appropriately controlling the doses of the first and second ion implantations. In this case, the threshold voltage Vth is not proportional to the dose and saturated at a high dose area despite the increase of dose, as shown in FIG. 5. Therefore, it is difficult to ensure the threshold voltages of the four states are at acceptable levels, especially, cells "10" and "11", which use two ion implantation steps. That is, the threshold voltage of the state "11" may drop below an acceptable level in the second ion implantation for the state "10". On the contrary, the threshold voltage of the state "10" may increase beyond an acceptable level in the second ion implantation for the state "11". Hence, there is difficulty in determining a read voltage for sensing each cell.
Since it is difficult to ensure the threshold voltages for the four states with two masks and two ion implantations as described above, impurities should be ion implanted using a program pattern for each state and three masks to achieve threshold voltages at intended levels. In view of the feature of ROMs, that is, entering data according to user demands prior to complete fabrication of ROMs, the competitiveness of the ROM products depends on how rapidly user demands are satisfied, that is, how short turnaround time is, as well as differential product characteristics. Therefore, an increase in the number of programming masks leads to a long mask fabrication time and adds to masking steps for these ROM products, thereby adversely influencing the turnaround time. In addition, ion implantation should be performed with a high dose to program the states "11" and "10". In this case, the ion implantation is to be performed in several steps because of constraints involved in ion implantation. Furthermore, three critical mask processes for programming may make it difficult to ensure process margin due to layer-to-layer misalignment. The threshold voltage distribution characteristics are deteriorated as the doping level of a channel region increases. Thus, the threshold voltage distribution characteristics of the states "11" and "10" may be deteriorated.